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IS34C02
2K-bit 2-WIRE SERIAL CMOS EEPROM with Permanent Write-Protection
ISSI
DESCRIPTION
(R)
ADVANCED INFORMATION JANUARY 2005
FEATURES
* Two-Wire Serial Interface, I2CTM compatible - Bidirectional data transfer protocol - 400 kHz (2.5V) and 1 MHz (5.0V) compatibility * Organization: - 256 x 8-bit * Data Protection Features - Write Protect Pin - Permanent Software Protection * 16-Byte Page Write Buffer - Partial Page-writes permitted * Low Power CMOS Technology - Active Current less than 2 mA (5V) - Standby Current less than 6 A (5V) - Standby Current less than 2 A (2.5V) * Low Voltage Operation - IS34C02-2: Vcc = 1.8V to 5.5V - IS34C02-3: Vcc = 2.5V to 5.5V * Random or Sequential Read Modes * Filtered Inputs for Noise Suppression * Self timed Write cycle with auto clear - 5 ms @ 2.5V * High Reliability - Endurance: 1,000,000 Cycles - Data Retention: 40 Years * Automotive and Industrial temperature ranges * 8-pin SOIC, 8-pin TSSOP, and 8-pin MSOP * Lead-free available
The IS34C02 is an electrically erasable PROM device that uses the standard 2-wire interface for communications. The IS34C02 contains a memory array of 2,048-bits (256K x 8), and is further subdivided into 16 pages of 16 bytes each for page-write mode. The software write-protection feature is initiated with a unique irreversible instruction. After this command is transmitted, the first 128 bytes of the array become permanently read-only. This feature is popular in applications like DRAM DIMMs to retain DRAM related data. This EEPROM is offered in wide operating voltages of 1.8V to 5.5V (IS34C02-2) and 2.5V to 5.5V (IS34C023) to be compatible with most application voltages. ISSI designed the IS34C02 as a low-cost and low-power 2wire EEPROM solution. The devices are packaged in 8-pin SOIC, and 8-pin TSSOP, and 8-pin MSOP. The IS34C02 maintains compatibility with the popular 2wire bus protocol, so it is easy to use in applications implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as the IS34C02. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS34C02 has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus.
Copyright (c) 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00E 01/12/05
1
IS34C02
ISSI
(R)
FUNCTIONAL BLOCK DIAGRAM
Vcc
HIGH VOLTAGE GENERATOR, TIMING & CONTROL
SDA WP SLAVE ADDRESS REGISTER & COMPARATOR A0 A1 A2 WORD ADDRESS COUNTER
X DECODER
SCL
CONTROL LOGIC
00H-7FH ARRAY 80H-FFH
Y DECODER
GND nMOS
ACK
Clock DI/O
>
DATA REGISTER
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00E 01/12/05
IS34C02
ISSI
(R)
PIN CONFIGURATION 8-Pin SOIC, TSSOP, MSOP
A0 A1 A2 GND
1 2 3 4
8 7 6 5
VCC WP SCL SDA
PIN DESCRIPTIONS
A0-A2 SDA SCL WP Vcc GND Address Inputs Serial Address/Data I/O Serial Clock Input Write Protect Input Power Supply Ground
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc, the entire array becomes Write Protected, and software writeprotection cannot be initiated. When WP is tied to GND or left floating, normal read/write operations are allowed to the device. If the device has already received a write-protection command, the memory in the range of 00h-7Fh is read -only regardless of the setting of the WP pin.
DEVICE OPERATION SCL
This input clock pin is used to synchronize the data transfer to and from the device. The IS34C02 features a serial communication and supports a bi-directional 2-wire bus transmission protocol called I2CTM.
SDA
The SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire Or'ed with other open drain or open collector outputs. The SDA bus requires a pullup resistor to Vcc.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and a Serial Clock line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving device as a receiver. The bus is controlled by Master device which generates the SCL, controls the bus access and generates the Stop and Start conditions. The IS34C02 is the Slave device on the bus.
A0, A1, A2
The A0, A1, and A2 are the device address inputs that are hardwired or left unconnected for hardware flexibility. When pins are hardwired, as many as eight devices may be addressed on a single bus system. When the pins are not hardwired, the default values of A0, A1, and A2 are zero.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00E 01/12/05
3
IS34C02
DEVICE ADDRESSING
ISSI
(R)
The Bus Protocol:
- Data transfer may be initiated only when the bus is not busy - During a data transfer, the SDA line must remain stable whenever the SCL line is high. Any changes in the SDA line while the SCL line is high will be interpreted as a Start or Stop condition. The state of the SDA line represents valid data after a Start condition. The SDA line must be stable for the duration of the High period of the clock signal. The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition.
The Master begins a transmission by sending a Start condition. The Master then sends the address of the particular Slave devices it is requesting. The Slave device (Fig. 5) address is 8 bits. The four most significant bits of the Slave device address are fixed as 1010 for normal read/write operations, and 0110 for permanent write-protection operations. This device has three address bits (A1, A2, and A0) that allow up to eight IS34C02 devices to share the 2-wire bus. Upon receiving the Slave address, the device compares the three address bits with the hardwired A2, A1, and A0 input pins to determine if it is the appropriate Slave. If any of the A2 - A0 pins is neither biased to High nor Low, internal circuitry defaults the value to Low. The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master transmits the Start condition and Slave address byte (Fig. 5), the appropriate 2-wire Slave (eg. IS34C02) will respond with ACK on the SDA line. The Slave will pull down the SDA on the ninth clock cycle, signaling that it received the eight bits of data. The selected IS34C02 then prepares for a Read or Write operation by monitoring the bus.
Start Condition
The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The IS34C02 monitors the SDA and SCL lines and will not respond until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must end with a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line.
Reset
The IS34C02 contains a reset function in case the 2wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The IS34C02 will enter standby mode: a) At Power-up, and remain in it until SCL or SDA toggles; b) Following the Stop signal if no write operation is initiated; or c) Following any internal write operation
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ADVANCED INFORMATION Rev. 00E 01/12/05
IS34C02
ISSI
Permanent Write Protection
(R)
WRITE OPERATION Byte Write
In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends a byte address that is written into the address pointer of the IS34C02. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS34C02 acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device.
The IS34C02 contains a permanent write protection feature that is initiated by means of a software command. After the command is transmitted, the protected area becomes irreversibly read-only despite power removal and reapplication on the device. The address range of the 128 bytes of the array that is affected by this feature is 00h-7Fh. Once enabled, the permanent protection is independent of the status of the WP pin. (If WP is raised to High, the entire array is read-only. If WP is low, the region 00h-7Fh can still be read-only.) The software command is initiated similarly to a normal byte write operation; however, the slave address begins with the bits 0110 (see Figure 5). The following three bits are A2 - A0. The last bit of the slave address (R/W) is 0. If the IS34C02 responds with ACK, the device has not yet had its write-protection permanently enabled. To complete the command, the Master must transmit a dummy address byte, dummy data byte, and a Stop signal (see Figure 11). The WP pin must be Low during this command. Before resuming any other command, the internal write cycle should be observed. The status of the permanent write protection can be safely determined without any changes by transmitting the same Slave address as above, but with the last bit (R/W) set to 1 (see Figure 12). If the permanent write protection has been enabled, the IS34C02 will not acknowledge any slave address starting with bits 0110 (see Figure 5).
Page Write
The IS34C02 is capable of 16-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data byte is transferred, the Master device can transmit up to 15 more bytes. After the receipt of each data byte, the IS34C02 responds immediately with an ACK on SDA line, and the four lower order data byte address bits are internally incremented by one, while the higher order bits of the data byte address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 16 bytes prior to issuing the Stop condition, the address counter will "roll over," and the previously written data will be overwritten. Once all 16 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS34C02 in a single Write cycle. All inputs are disabled until completion of the internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host's Write operation, the IS34C02 initiates the internal Write cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave address for a Write operation. If the IS34C02 is still busy with the Write operation, no ACK will be returned. If the IS34C02 has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation.
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ADVANCED INFORMATION Rev. 00E 01/12/05
5
IS34C02
ISSI
Sequential Read
(R)
READ OPERATION
Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to "1". There are three Read operation options: current address read, random address read and sequential read.
Current Address Read
The IS34C02 contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the IS34C02 receives the Device Addressing Byte with a Read operation (R/W bit set to "1"), it will respond an ACK and transmit the 8-bit data byte stored at address location n+1. The Master should not acknowledge the transfer but should generate a Stop condition so the IS34C02 discontinues transmission. If the last byte of the memory was the previous access, the data from location '0' will be transmitted. (Refer to Figure 8. Current Address Read Diagram.)
Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS34C02 sends the initial byte sequence, the Master device responds with an ACK indicating it requires additional data from the IS34C02. The IS34C02 continues to output data for each ACK received. The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data byte to be read, followed by a Stop condition. The data output is sequential, with the data from address n followed by the data from address n+1, ... etc. The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operations. When the memory address boundary 255 is reached, the address counter "rolls over" to address 0, and the IS34C02 continues to output data for each ACK received. (Refer to Figure 10. Sequential Read Operation Starting with a Random Address Read Diagram.)
Random Address Read
Selective Read operations allow the Master device to select at random any memory location for a Read operation. The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave address and word address of the location it wishes to read. After the IS34C02 acknowledges the word address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one. The IS34C02 then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition. (Refer to Figure 9. Random Address Read Diagram.)
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Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00E 01/12/05
IS34C02
ISSI
Vcc
(R)
Figure 1. Typical System Bus Configuration
SDA SCL
Master Transmitter/ Receiver
IS34C02
Figure 2. Output Acknowledge
SCL from Master
1
8
9
Data Output from Transmitter
tAA tAA
Data Output from Receiver
ACK
Figure 3. Start and Stop Conditions
STOP Condition
SDA
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ADVANCED INFORMATION Rev. 00E 01/12/05
START Condition
SCL
7
IS34C02
ISSI
Data Change
(R)
Figure 4. Data Validity Protocol
SCL
Data Stable Data Stable
SDA
Figure 5. Slave Address
BIT 7 6 5 4 3 2 1 0
1
BIT 7
0
6
1
5
0
4
A2
3
A1
2
A0
1
R/W
0
Normal Instruction
0
1
1
0
A2
A1
A0
R/W
Permanent Write Protect Instruction
Figure 6. Byte Write
S T A R T W R I T E* A C K L S B R/W S T O *P A C K
Device Address
Word Address
*
A C K
Data
SDA Bus Activity
M S B
M S B
* Acknowledges provided by the slave regardless of hardware or software Write Protection.
Figure 7. Page Write
S T A R T W R I T E * Word Address (n) * A A C C K K L S B R/W S T O *P A C K
Device Address
Data (n)
SDA Bus Activity
* A C K
Data (n+1)
* A C K
Data (n+15)
M S B
* Acknowledges provided by the slave regardless of hardware or software Write Protection.
8
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ADVANCED INFORMATION Rev. 00E 01/12/05
IS34C02
ISSI
S T A R T SDA Bus Activity M S B L S B R/W R E A D A C K N O A C K S T O P
(R)
Figure 8. Current Address Read
Device Address
Data
Figure 9. Random Address Read
S T A R T SDA Bus Activity M S B W R I T E A C K L S B R/W DUMMY WRITE S T A R T A C K
Device Address
Word Address (n)
Device Address
R E A D A C K
Data n
S T O P
N O A C K
Figure 10. Sequential Read
R E A D A C K S T O P
Device Address SDA Bus Activity
Data Byte n A C K
Data Byte n+1 A C K
Data Byte n+2 A C K
Data Byte n+X
N O R/W A C K
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ADVANCED INFORMATION Rev. 00E 01/12/05
9
IS34C02
ISSI
(R)
FIGURE 11. PERMANENT WRITE PROTECTION INITIATION
SDA Bus Activity
S T A R T
W R I Device T Data Address E * Word Address A A A C # # ## # # # #C # # # ## # # # C K K K M L M S S S B B B R/W
S T O P
* The slave does not provide an acknowledgement if the permanent write protection is already enabled. # Don't care bits are required.
FIGURE 12. PERMANENT WRITE PROTECTION VERIFICATION
S T A R T SDA Bus Activity M S B
Device Address
RS ET AO D*P A C K L S B R/W
* The slave does not provide an acknowledgement if the permanent write protection is already enabled.
10
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ADVANCED INFORMATION Rev. 00E 01/12/05
IS34C02
ISSI
Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value -0.5 to +6.5 -0.5 to Vcc + 0.5 -55 to +125 -65 to +150 5 Unit V V C C mA
(R)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VS VP TBIAS TSTG IOUT
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
(IS34C02-2) Range Industrial Ambient Temperature -40C to +85C VCC 1.8V to 5.5V
OPERATING RANGE
(IS34C02-3) Range Automotive Ambient Temperature -40C to +125C VCC 2.5V to 5.5V
Note: Automotive data is preliminary.
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V.
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ADVANCED INFORMATION Rev. 00E 01/12/05
11
IS34C02
DC ELECTRICAL CHARACTERISTICS
Industrial (TA = -40oC to +85oC), Automotive (TA = -40oC to +125oC)
Symbol VOL1 VOL2 VIH VIL ILI ILO Parameter Output Low Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Test Conditions VCC = 1.8V, IOL = 0.15 mA VCC = 2.5V, IOL = 3 mA
ISSI
Min. Max. -- 0.2 -- 0.4 VCC X 0.7 VCC + 0.5 -1.0 VCC X 0.3 -- 3 -- 3 Unit V V V V A A
(R)
VIN = VCC max.
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS
Industrial (TA = -40oC to +85oC), Automotive (TA = -40oC to +125oC)
Symbol ICC1 ICC2 ISB1 ISB2 ISB3 Parameter Vcc Operating Current Vcc Operating Current Standby Current Standby Current Standby Current Test Conditions Read at 400 KHz (Vcc = 5V) Write at 400 KHz (Vcc = 5V) Vcc = 1.8V Vcc = 2.5V Vcc = 5.0V Min. -- -- -- -- -- Max. 2.0 3.0 1 2 6 Unit mA mA A A A
AC ELECTRICAL CHARACTERISTICS
Industrial (TA = -40oC to +85oC)
1.8V-5.5V Symbol fSCL T tLow tHigh tBUF tSU:STA tSU:STO tHD:STA tHD:STO tSU:DAT tHD:DAT tSU:WP tHD:WP tDH tAA tR tF tWR Parameter SCL Clock Frequency Noise Suppression Time(1) Clock Low Period Clock High Period Bus Free Time Before New Transmission(1) Start Condition Setup Time Stop Condition Setup Time Start Condition Hold Time Stop Condition Hold Time Data In Setup Time Data In Hold Time WP pin Setup Time WP pin Hold Time Data Out Hold Time (SCL Low to SDA Data Out Change) Clock to Output (SCL Low to SDA Data Out Valid) SCL and SDA Rise Time(1) SCL and SDA Fall Time(1) Write Cycle Time Min. Max. 0 100 -- 100 4.7 -- 4 -- 4.7 -- 4 -- 4 -- 4 -- 4 -- 100 -- 0 -- 4 -- 4.7 -- 100 -- 100 3500 -- 1000 -- 300 -- 10 2.5V-5.5V Min. Max. 0 400 -- 50 1.2 -- 0.6 -- 1.2 -- 0.6 -- 0.6 -- 0.6 -- 0.6 -- 100 -- 0 -- 0.6 -- 1.2 -- 50 -- 50 900 -- 300 -- 300 -- 5 4.5V-5.5V(1) Min. Max. 0 1000 -- 50 0.6 -- 0.4 -- 0.5 -- 0.25 -- 0.25 -- 0.25 -- 0.25 -- 100 -- 0 -- 0.6 -- 1.2 -- 50 -- 50 400 -- 300 -- 100 -- 5 Unit KHz ns s s s s s s s ns ns s s ns ns ns ns ms
Note: 1. These parameters are characterized, but not 100% tested. 2. The device IS34C02-2 is tested to meet the timing values of both 1.8V-5.5V and 2.5V-5.5V.
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ADVANCED INFORMATION Rev. 00E 01/12/05
IS34C02
AC ELECTRICAL CHARACTERISTICS
Automotive (TA = -40oC to +125oC)
2.5V-5.5V Symbol Parameter fSCL T tLow tHigh tBUF tSU:STA tSU:STO tHD:STA tHD:STO tSU:DAT tHD:DAT tSU:WP tHD:WP tDH tAA tR tF tWR SCL Clock Frequency Noise Suppression Time(1) Clock Low Period Clock High Period Bus Free Time Before New Transmission(1) Start Condition Setup Time Stop Condition Setup Time Start Condition Hold Time Stop Condition Hold Time Data In Setup Time Data In Hold Time WP pin Setup Time WP pin Hold Time Data Out Hold Time (SCL Low to SDA Data Out Change) Clock to Output (SCL Low to SDA Data Out Valid) SCL and SDA Rise Write Cycle Time Time(1) SCL and SDA Fall Time(1) Min. Max. 0 -- 1.2 0.6 1.2 0.6 0.6 0.6 0.6 100 0 0.6 1.2 50 50 -- -- -- 400 50 -- -- -- -- -- -- -- -- -- -- -- -- 900 300 300 10 4.5V-5.5V(1) Min. Max. 0 -- 0.6 0.4 0.5 0.25 0.25 0.25 0.25 100 0 0.6 1.2 50 50 -- -- -- 1000 50 -- -- -- -- -- -- -- -- -- -- -- -- 550 300 100 5 Unit KHz ns s s s s s s s ns ns s s ns ns ns ns ms
ISSI
(R)
Note: 1. These parameters are characterized but not 100% tested.
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ADVANCED INFORMATION Rev. 00E 01/12/05
13
IS34C02
ISSI
(R)
FIGURE 13. AC WAVEFORMS
tR
tF
tHIGH
tLOW
tSU:STO
SCL
tSU:STA tHD:STA tHD:DAT tSU:DAT tBUF
SDAIN
tAA
tDH
SDAOUT
tSU:WP
tHD:WP
WP
FIGURE 14. WRITE CYCLE TIMING
SCL
SDA
8th BIT WORD n
ACK
tWR
STOP Condition START Condition
14
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00E 01/12/05
IS34C02
ISSI
Voltage Range 1.8V to 5.5V
(R)
ORDERING INFORMATION Industrial Range: -40C to +85C, Lead-free
Frequency 100 KHz Part Number IS34C02-2GLI IS34C02-2SLI IS34C02-2ZLI Package Small Outline (JEDEC STD) (8-pin) MSOP TSSOP
Note: The specification allows for higher speed. Please see AC Characteristics (2.5V-5.5V or 4.5V-5.5V)
Industrial Range: -40C to +85C
Frequency 100 KHz Voltage Range 1.8V to 5.5V Part Number IS34C02-2GI IS34C02-2SI IS34C02-2ZI Package Small Outline (JEDEC STD) (8-pin) MSOP TSSOP
Note: The specification allows for higher speed. Please see AC Characteristics (2.5V-5.5V or 4.5V-5.5V)
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
ADVANCED INFORMATION Rev. 00E 01/12/05
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